74HC163 IC – (SMD Package) – Presettable synchronous Binary counter IC (74163)

The 74HC163; 74HCT163 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action. It causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW after the next positive-going transition

SKU: RW-01951

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Description

The 74HC163; 74HCT163 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action. It causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW after the next positive-going transition

on the clock input (CP). This action occurs regardless of the levels at input pins PE, CET and CEP. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC


Features :-

  • Complies with JEDEC standard no. 7A
  • Input levels:

                For 74HC163: CMOS level

                For 74HCT163: TTL level

  • Synchronous counting and loading
  • 2 count enable inputs for n-bit cascading
  • Synchronous reset
  • Positive-edge triggered clock
  • ESD protection:

                HBM JESD22-A114F exceeds 2 000 V

                MM JESD22-A115-A exceeds 200 V

  • Multiple package options
  • Specified from -40 ?C to +85 ?C and -40 ?C to +125 ?C


Specifications :-

Parameter

Min

Max

Unit

Supply voltage

 -0.5

 +7.0

V

Input clamp current

 –

+20

mA

Output clamp current

 –

+20

mA

output current

 –

+25

mA

supply current

         –

      
 50

mA

ground current

     
-50

         –

   mA

storage temperature

      -65

     +150

   ?C

total power dissipation

        –

         500

 mW


Package Includes :-

1 X 74HC163 Presettable Synchronous 4-bit Binary Counter IC (74163 IC) DIP-16 Package

Additional information

Operating voltage

2.5 3.0V

Pixel Resolution

0.3MP

Photosensitive array

640 x 480

Optical Size

1.6 inch

Angel of view

67 degrees

Maximum Frame Rate

30fps VGA

Sensitivity

1.3V/(Lux-sec)

Dormancy

Less than 20A

Power consumption

60mW/15fpsVGA YUV

Temperature operation Range

-30 C ~ 70 C

Pixel area

3.6 x 3.6 m

Signal to noise ratio (SNR)

46 dB

Dynamic range

52 dB

Specification

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