ICs & Dips

This data selector/multiplexer contains full on-chip decoding to select the desired data source. The 74LS151 selects one-of-eight data sources. The 74LS151 has a strobe input which must be at a low logic level to enable these devices. A high level at the strobe forces the W output HIGH, and the Y output LOW. The 74LS151 features complementary W and Y outputs.

In 74LS153 IC, Each of these data selectors/multiplexers contains inverters and drivers to supply fully complementary, on-chip, binary decoding data selection to the AND-OR-invert gates. Separate strobe inputs are provided for each of the two four-line sections. 

The 74LS153 is a very high speed Dual 4-Input Multiplexer with common select inputs and individual enable inputs for each section. It can select two bits of data from four sources. The two buffered outputs present data in the true (non-inverted) form. In addition to multiplexer operation, the LS153 can generate any two functions of three variables. The LS153 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families. The following are the features:-

In 74LS154 IC, Each of these 4-line-to-16-line decoders utilizes TTL circuitry to decode four binary-coded inputs into one of sixteen mutually exclusive outputs when both the strobe inputs, G1 and G2, are LOW. The demultiplexing function is performed by using the 4 input lines to address the output line, passing data from one of the strobe inputs with the other strobe input LOW. When either strobe input is HIGH, all outputs are HIGH. These demultiplexers are ideally suited for implementing high-performance memory decoders. All inputs are buffered and input clamping diodes are provided to minimize transmission-line effects and thereby simplify system design. 

The 74LS158 is a high speed Quad 2-input Multiplexer. It selects four bits of data from two sources using the common Select and Enable inputs. The four buffered outputs present the selected data in the inverted form. The LS158 can also generate any four of the 16 different functions of two variables. The LS158 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families

74LS161 4-Bit Binary Counter IC circuit designed as a synchronous reversible up-down counter. These synchronous, presettable counters provide an internal carry look-ahead feature for application in high-speed counting designs. The carry output decoded via a NOR gate. Thus preventing spikes during the normal counting mode of operation 74LS161 comes with a 4-bit binary counter in which Synchronous operation provided by all flip-flops clocked simultaneously. As a result, the outputs change simultaneously as instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) fringe of the clock input waveform.

74LS161 4-Bit Binary Counter IC circuit designed as a synchronous reversible up-down counter. These synchronous, presettable counters provide an internal carry look-ahead feature for application in high-speed counting designs. The carry output decoded via a NOR gate. Thus preventing spikes during the normal counting mode of operation 74LS161 comes with a 4-bit binary counter in which Synchronous operation provided by all flip-flops clocked simultaneously. As a result, the outputs change simultaneously as instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) fringe of the clock input waveform.

The 74LS166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 74LS standard load. By utilizing input clamping diodes, switching transients are minimized and system design simplified. The LS166 is a parallel-in or serial-in, serial-out shift register and has a complexity of 77 equivalent gates with gated clock inputs and an overriding clear input. The shift/load input establishes the parallel-in or serial-in mode. When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. Synchronous loading occurs on the next clock pulse when this is low and the parallel data inputs are enabled. Serial data flow is inhibited during parallel loading. Clocking is done on the low-to-high level edge of the clock pulse via a two input positive NOR gate, which permits one input to be used as a clock enable or clock inhibit function. Clocking is inhibited when either of the clock inputs are held high, holding either input low enables the other clock input. This will allow the system clock to be free running and the register stopped on command with the other clock input. A change from low-to-high on the clock inhibit input should only be done when the clock input is high. A buffered direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero.