ICs & Dips

The 74LS280 IC designed as a Universal 9-Bit Parity Generator /Checker. These IC provides odd/ even outputs to facilitate either odd or even parity. By cascading, the word length is easily expanded. The 74LS280 IC operates at a wide range of working voltage, a wide range of working conditions. And directly interfaces with CMOS, NMOS, and TTL. The output of the IC always comes in TTL which makes it quite easy to function with other TTL devices and microcontrollers. The IC 74LS280 comes as smaller in size and offers much faster speed which makes it highly reliable in every kind of device.

The 74LS290 are high-speed 4-bit ripple type counters partitioned into two sections. Each counter has a divide-by-two section and either a divide-by-five (LS290) or divide-by-eight (LS293) section which are triggered by a HIGH-to-LOW transition on the clock inputs. Each section can be used separately or tied together (Q to CP)to form BCD, Bi-quinary, or Modulo-16 counters. Both of the counters have a 2-input gated Master Reset (Clear), and the LS290 also has a 2-input gated Master Set (Preset 9).

The 74LS290 are high-speed 4-bit ripple type counters partitioned into two sections. Each counter has a divide-by-two section and either a divide-by-five (LS290) or divide-by-eight (LS293) section which are triggered by a HIGH-to-LOW transition on the clock inputs. Each section can be used separately or tied together (Q to CP)to form BCD, Bi-quinary, or Modulo-16 counters. Both of the counters have a 2-input gated Master Reset (Clear), and the LS290 also has a 2-input gated Master Set (Preset 9).

The 74LS298 is a Quad 2-Port Register. It is the logical equivalent of a quad 2-input multiplexer followed by a quad 4-bit edge-triggered register. A Common Select input selects between two 4-bit input ports (data sources.) The selected data is transferred to the output register synchronous with the HIGH to LOW transition of the 

The 74LS299 is an 8-bit universal shift/storage register with 3-STATE outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Separate outputs are provided for flip-flops Q0 and Q7 to allow easy cascading. A separate active LOW Master Reset is used to reset the register

These LS31 delay elements are intended to provide well-defined delays across both temperature and VCC ranges. Used in cascade, a limitless range of delay gating is possible. All inputs are PNP with IL MAX of -0.2 mA. Gates 1, 2, 5, and 6 have standard Low-Power Schottky output sink current capability of 4 and 8 mA IOL Buffers 3 and 4 are rated at 12 and 24 mA. The 74LS31 is characterized for operation from 0?C to 70?C

These LS31 delay elements are intended to provide well-defined delays across both temperature and VCC ranges. Used in cascade, a limitless range of delay gating is possible. All inputs are PNP with IL MAX of -0.2 mA. Gates 1, 2, 5, and 6 have standard Low-Power Schottky output sink current capability of 4 and 8 mA IOL Buffers 3 and 4 are rated at 12 and 24 mA. The 74LS31 is characterized for operation from 0?C to 70?C

The 74LS32 is a 14 Pin Quad 2-Input OR Gate IC. The 74LS32 provides four independent 2-input OR gates with standard push-pull