ICs & Dips

The 74LS74 device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as the data setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. 

The 74LS74 device contain two independent D-type Positive Edge-triggered flip-flops. A low level at preset or clear inputs sets or resets the output regardless of the levels of the other inputs. When preset and clear are inactive(high), data at the D input meeting the setup time requirements are transferred to the output on the positive-going edge of the clock pulse. Following the hold time interval, data at the D input maybe changed  without affecting the levels at the output. The 74LS74 is characterized for operation from O? C to 70? C.

The 74LS76 offers individual J, K, Clock Pulse, Direct Set and Direct Clear inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The Logic Level of the J and K inputs will perform according to the Truth Table as long as minimum set-up times are observed. Input data is transferred to the outputs on the HIGH-to-LOW clock transitions.

74LS90 Decade Counter IC having 4.75 to 5.25V Supply Voltage with 8mA Low Level and - 0.4mA High Level Output Current. It is a simple counter, it can count from 0 to 9 cyclically in its natural mode. It counts the input pulses and the output is received as a 4-bit binary number through pins QA, QB, QC and QD. The binary output is reset to 0000 at every tenth pulse and count starts from 0 again. 

The 74LS95 is a 4-Bit Shift Register with serial and parallel synchronous operating modes. The serial shift right and parallel load are activated by separate clock inputs which are selected by a mode control input. The data is transferred from the serial or parallel D inputs to the Q outputs synchronous with the HIGH to LOW transition of the appropriate clock input. The 74LS95 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families. The following are the features:-

The 74LS96 is a 5-bit shift register with both serial and parallel (ones transfer) data entry. Since the '96 has the output of each stage available as well as a D-type serial input and ones transfer inputs on each stage, it can be used 5-bit serial- to-parallel, serial-to-serial and some parallel-to-serial data operations. The 74LS96 is five master/slave flip-flops connected to perform right shift. The flip- flops change state on the LOW-HIGH transition of the clock. The Serial (S) input is edge-triggered and must be stable only one set-up time before the LOW to HIGH clock transition.

The 74LS96 is a  shift registers consist of five RS master-slave flip-flops connected to perform parallel-to-serial or serial to parallel conversion of binary data. Since both inputs and outputs for all flip-flops are accessible parallel-in/parallel-out  serial in/serial out operation may be performed.

These circuits are TRI-STATE, edge-triggered, 8-bit I/O registers in parallel with 8-bit serial shift registers which are capable of operating in any of the following modes: parallel load from I/O pins to register ??A??, parallel transfer down from register ??A?? to serial shift register ??B??, parallel transfer up from shift register ??B?? to register ??A??, serial shift of register ??B??, or exchange data between register ??A?? and shift register ??B??. Since the registers are edge-triggered by the positive transition of the clock, the control lines which determine the mode or operation are completely independent of the logic level applied to the clock. Designed for bus-oriented systems, these circuits have their TRI-STATE inputs and outputs on the same pins.