ICs & Dips

The 74HC137 decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications.

The 74HC137 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC137 is specified in compliance with JEDEC

The 74HC138 decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications. The circuit features high noise immunity and low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky TTL logic. The 74HC138 has 3 binary select inputs (A, B, and C). If the device is enabled, these inputs determine which one of the eight normally HIGH outputs will go LOW. Two active LOW and one active HIGH enables (G1, G2A and G2B) are provided to ease the cascading of decoders. The decoder?s outputs can drive 10 low power Schottky TTL equivalent loads, and are functionally and pin equivalent to the 74LS138. All inputs are protected from damage due to static discharge by diodes to VCC and ground.

The 74HC138 decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications. The circuit features high noise immunity and low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky TTL logic. The 74HC138  has 3 binary select inputs (A, B, and C). If the device is enabled, these inputs determine which one of the eight normally HIGH outputs will go LOW. Two active LOW and one active HIGH enables (G1, G2A and G2B) are provided to ease the cascading of decoders. The decoder?s outputs can drive 10 low power Schottky TTL equivalent loads, and are functionally and pin equivalent to the 74LS138. All inputs are protected from damage due to static discharge by diodes to VCC and ground.

74HC151 is 8 - Input Multiplexer 16 Pin IC. Data Selector/Multiplexer contains full on-chip decoding to select one-of-eight data sources as a result of a unique three binary code at select inputs. Two complementary outputs provide both inverting and non-inverting buffer operation. A Strobe input is provided which, when at  high level, disables all data inputs and forces Y output to low state and W output to high state. Select input buffers incorporate internal overlap features to ensure that select input changes do not cause invalid output transients.Used for Boolean Function Generator.

The 74HC151 high speed Digital multiplexer utilizes advanced silicon-gate CMOS technology. Along with the high noise immunity and low power dissipation of standard CMOS integrated circuits, it possesses the ability to drive 10 LS-TTL loads. The 74HC151 selects one of the 8 data sources, depending on the address presented on the A, B, and C inputs. It features both true (Y) and complement (W) outputs. The STROBE input must be at a low logic level to enable this multiplexer. A high logic level at the STROBE forces the W output HIGH and the Y output LOW. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.  

The 74HC154 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications. It possesses high noise immunity, and low power consumption of CMOS with speeds similar to low power Schottky TTL circuits. The 74HC154 have 4 binary select inputs (A, B, C, and D). If the device is enabled these inputs determine which one of the 16 normally HIGH outputs will go LOW. Two active LOW enables (G1 and G2) are provided to ease cascading of decoders with little or no external logic. Each output can drive 10 low power Schottky TTL equivalent loads, and is functionally and pin equivalent to the 74LS154. All inputs are protected from damage due to static discharge by diodes to VCC and ground. 

The 74HC157 is identical in pinout to the LS157. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device routes 2 nibbles (A or B) to a single port (Y) as determined by the Select input. The data is presented at the outputs in non inverted form. A high level on the Output Enable input sets all four Y outputs to a low level. The 74HC157 is similar in function to the HC257 which has 3?state output.