74F109 Positive J-K Positive Edge-Triggered Flip-Flops IC (74109) DIP-16 Package

The 74F109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock (CP) input. The J and K are edge-triggered inputs which control the state changes of the flip-flops as described in the function table. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. The J and K inputs must be stable just one setup time prior to the low-to-high transition of the clock for predictable operation. The JK design allows operation as a D flip-flop by tying J and K inputs together. Although the clock input is level sensitive, the positive transition of the clock pulse between the 0.8V and 2.0V levels should be equal to or less than the clock to output delay time for reliable operation

Features :-

Industrial temperature range available (?40?C to +85?C)

Specifications :-

• Supply voltage : ?0.5 to +7.0V
• Input voltage : ?0.5 to +7.0V
• Input current : ?30 to +5mA
• Voltage applied to output in High output state : ?0.5V to VCC
• Current applied to output in Low output state : 40mA
• Operating free air temperature range (Commercial range) : 0 to +70?C 
• Operating free air temperature range (Industrial range) : ?40 to +85?C 
• Storage temperature range : ?65 to +150?C

Package Includes :-

1 X 74F109 Positive J-K Positive Edge-Triggered Flip-Flops IC (74109) DIP-16 Package