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The 74LS173 is a 4-bit registers include D-type flip-flops featuring totem-pole 3-state outputs capable of driving highly capacitive or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide these flip-flops with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. Up to 128 of the 74LS173 outputs can be connected to a common bus and still drive two Series 74LS TTL normalized loads, respectively. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the output control circuitry is designed so that the average output disable times are shorter than the average output enable times. Gated enable inputs are provided on these devices for controlling the entry of data into the flip-flops. When both data-enable (G1, G2) inputs are low, data at the D inputs are loaded into their respective flip-flops on the next positive transition of the buffered clock input. Gate output-control (M, N) inputs also are provided. When both are low, the normal logic states (high or low levels) of the four outputs are available for driving the loads or bus lines. The outputs are disabled independently from the level of the clock by a high logic level at either output-control input. The outputs then present a high impedance and neither load nor drive the bus line. Detailed operation is given in the function table. The 74LS173 is characterized for operation from 0?C to 70?C .
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Our courier will deliver to the specified address
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courier will deliver to the specified address
5-7 Days
90
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The 74LS173 is a 4-bit registers include D-type flip-flops featuring totem-pole 3-state outputs capable of driving highly capacitive or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide these flip-flops with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. Up to 128 of the 74LS173 outputs can be connected to a common bus and still drive two Series 74LS TTL normalized loads, respectively. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the output control circuitry is designed so that the average output disable times are shorter than the average output enable times. Gated enable inputs are provided on these devices for controlling the entry of data into the flip-flops. When both data-enable (G1, G2) inputs are low, data at the D inputs are loaded into their respective flip-flops on the next positive transition of the buffered clock input. Gate output-control (M, N) inputs also are provided. When both are low, the normal logic states (high or low levels) of the four outputs are available for driving the loads or bus lines. The outputs are disabled independently from the level of the clock by a high logic level at either output-control input. The outputs then present a high impedance and neither load nor drive the bus line. Detailed operation is given in the function table. The 74LS173 is characterized for operation from 0?C to 70?C .
Features:-
? 3-State Outputs Interface Directly With System Bus
? Gated Output-Control Lines for Enabling or Disabling the Outputs
? Fully Independent Clock Virtually Eliminates Restrictions for Operating in One of Two Modes: ? Parallel Load ? Do Nothing (Hold)
? For Application as Bus Buffer Registers
? Package Options Include Plastic Small-Outline (D) Packages, Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J)
Specifications:-
Symbol | Parameter | Min | Type | Max | Unit | |
VCC | Supply Voltage | 4.75 | 5 | 5.25 | V | |
TA | Operation free-air temperature | -5.2 |
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IOH | Output Current ? High | 16 | mA | |||
IOL | Output Current ? Low | 0 | 70 |
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Package Includes :-
Operating voltage | 2.5 3.0V |
Pixel Resolution | 0.3MP |
Photosensitive array | 640 x 480 |
Optical Size | 1.6 inch |
Angel of view | 67 degrees |
Maximum Frame Rate | 30fps VGA |
Sensitivity | 1.3V/(Lux-sec) |
Dormancy | Less than 20A |
Power consumption | 60mW/15fpsVGA YUV |
Temperature operation Range | -30 C ~ 70 C |
Pixel area | 3.6 x 3.6 m |
Signal to noise ratio (SNR) | 46 dB |
Dynamic range | 52 dB |
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