ICs & Dips

The 6N136 is an optocoupler with a GaAIAs infrared emitting diode, optically coupled with an integrated photo detector which consists of a photo diode and a high-speed transistor in a DIP8 plastic package. Signals can be transmitted between two electrically separated circuits up to frequencies of 2 MHz. The potential difference between the circuits to be coupled should not exceed the maximum permissible reference voltages.

The 6N137 is single channel 10 MBd opto-couplers utilizing a high efficient input LED coupled with an integrated optical photodiode IC detector. The detector has an open drain NMOS-transistor output, providing less leakage compared to an open collector Schottky clamped transistor output. For the single channel type, an enable function on pin 7 allows the detector to be strobed. The use of a 0.1 ?F bypass capacitor connected between pin 5 and 8 is recommended.

The 6N138 consists of a GaA?As infrared emitting diode coupled with a split-Darlington output configuration. A high speed GaA?As Ired manufactured with an unique LPE junction, has the virtue of fast rise and fall time at low drive current.

6N139 High Speed Opto-coupler is High common mode transient immunity and very high current ratio together with 5300 VRMS insulation are achieved by coupling and LED with an integrated high gain photo detector in an eight pin dual-in-line package. Separate pins for the photo diode and output stage enable TTL compatible saturation voltages with high speed operation. Access to the base terminal allows adjustment to the gain bandwidth. The 6N138 is ideal for TTL applications since the 300 % minimum current transfer ratio with an LED current of 1.6 mA enables operation with one unit load-in and one unit load-out with a 2.2 kO pull-up resistor. The 6N139 optocoupler is best suited for low power logic applications involving CMOS and low power TTL. A 400 % current transfer ratio with only 0.5 mA of LED current is guaranteed from 0 ?C to 70 ?C.

The 74595 consists of an 8?bit shift register and an 8?bit D?type latch with three?state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8?bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register. The 74595 directly interfaces with the SPI serial data port on CMOS MPUs and MCUs. 

The 74F109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock (CP) input. The J and K are edge-triggered inputs which control the state changes of the flip-flops as described in the function table. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. The J and K inputs must be stable just one setup time prior to the low-to-high transition of the clock for predictable operation. The JK design allows operation as a D flip-flop by tying J and K inputs together. Although the clock input is level sensitive, the positive transition of the clock pulse between the 0.8V and 2.0V levels should be equal to or less than the clock to output delay time for reliable operation

The  74F113  offers  individual  J,  K,  Set  and  Clock  inputs. When  the  clock  goes  HIGH  the  inputs  are  enabled  and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flip-flop  will  perform  according  to  the  Truth  Table  as  long  as minimum setup and hold times are observed. Input data is transferred  to  the  outputs  on  the  falling  edge  of  the  clock pulse.

The 74F138 decoder accepts three binary weighted inputs (A0, A1, A2) and when enabled, provides eight mutually exclusive, active low outputs (Q0 ? Q7). The device features three enable inputs; two active low (E0, E1) and one active high (E2). Every output will be high unless E0 and E1 are low and E2 is high. This multiple enable function allows easy parallel expansion of the device to 1?of?32 (5 lines to 32 lines) decoder with just four 74F138s and one inverter The device can be used as an eight output demultiplexer by using one of the active low enable inputs as the data input and the remaining enable inputs as strobes. Enable inputs not used must be permanently tied to their appropriate active high or active low state.