Showing 289–300 of 418 results
74HC253 IC – (SMD Package) Dual 4-Bit Multiplexer IC (74253 IC)
The 74HC253 are high-speed Si-gate CMOS device sand are pin compatible with low power Schottky TTL(LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC253 have two identical 4-input multiplexer switch 3-state outputs which select two bits from four sources selected by common data select inputs (S0,S1).When the individual output enable (1OE, 2OE) inputs of the 4-input multiplexers are HIGH, the outputs are forced to the high impedance OFF-state. The ?253? is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels applied to S0and S1.
74HC258 IC – (SMD Package) Quad 2-input multiplexer IC (74258 IC)
The 74HC258 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC258 is specified in compliance with JEDEC standard no. 7A. The 74HC258 has four identical 2-input multiplexers with 3-state outputs, which select 4 bits of data from two sources and is controlled by a common data select input (S). The data inputs from source 0 (1I0 to 4I0) are selected when input S is LOW and the data inputs from source 1 (1I1 to 4I1) are selected when S is HIGH. Data appears at the outputs (1Y to 4Y) in inverted form from the select inputs. The 74HC258 is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to S. The outputs are forced to a high-impedance OFF-state when OE is HIGH.
74HC280 IC – (SMD Package) 9-bit Parity Generator IC (74280 IC)
The 74HC280 is a 9-bit parity generator or checker. Both even and odd parity outputs are available. The even parity output (PE) is HIGH when an even number of data inputs (I0 to I8)is HIGH. The odd parity output (PO) is HIGH when an odd number of data inputs are HIGH .Expansion to larger word sizes is accomplished by tying the even outputs (PE) of up to nine parallel devices to the final stage data inputs. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
74HC292 IC – (SMD Package) – High Speed CMOS Programmable Divider Timer IC (74292 IC)
The 74HC292/7292 and HC294/7294 are high speed CMOS PROGRAMMABLE DIVIDER/TIMER fabricated with silicon C2 MOS technology. They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. These devices are programmable frequency dividers. The type shave two clock inputs, either one may be used for clock gating. (see the function table). The HC292/7292 can divide from 22 to 231, and the HC294/7294 can divide from 22 to 215. The types feature an active-low clear input to initialize the state of all flip-flops. To facilitate incoming inspection, test points are provided. (TP1, TP2 and TP3 on the HC292/7292 and TP on the HC294/7294). All inputs are equipped with protection circuits against static discharge and transient excess voltage. HC292/294 have Q output with ?Totem pole? configuration and test point TP with ?Open Drain? output configuration.
74HC366 IC – (SMD Package) – Hex Inverting Buffer Line Driver IC (74366 IC)
74HC368 IC – (SMD Package) – Hex Inverting Buffer Line Driver IC (74368 IC)
The 74HC368; 74HCT368 is a hex inverting buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Inputs include clamp diodes enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
74HC4002 IC – (SMD Package) – Dual 4-input NOR Gate IC (744002 IC)
74HC40105 IC – (SMD Package) – 4-Bit x 16-Word FIFO Register IC (7440105)
The 74HC40105 is a first-in/first-out (FIFO) "elastic" storage register that can store 16 4-bit words. It can handle input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. A logic 1 signifies that the data at that position is filled and a logic 0 denotes a vacancy in that position. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the logic 0 state and sees a logic 1 in the preceding flip-flop, it generates a clock pulse. The clock pulse transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to logic 0. The first and last control flip-flops have buffered outputs. All empty locations "bubble" automatically to the input end, and all valid data ripples through to the output end. As a result, the status of the first control flip-flop (data-in ready output - DIR) indicates if the FIFO is full. The status of the last flip-flop (data-out ready output - DOR) indicates whether the FIFO contains data. As the earliest data is removed from the bottom of the data stack (output end), all data entered later will automatically ripple toward the output. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
74HC4016 IC – (SMD Package) – Quad Analog Switch Multiplexer Demultiplexer IC (744016 IC)
The 74HC4016 is a quad single pole, single throw analog switch. Each switch features two input/output terminals (nY and nZ) and an active HIGH enable input (nE). When nE is LOW, the analog switch is turned off. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
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