All Products

This device contains six independent gates each of which performs the logic INVERT function. The open-collector outputs require external pull-up resistors for proper logical operation.

This device contains six independent gates each of which performs the logic INVERT function. The open-collector outputs require external pull-up resistors for proper logical operation.

This 74LS06 monolithic hex inverter buffers/drivers feature high-voltage open-collector outputs to interface with high-level circuits (such as MOS), or for driving high-current loads, and are also characterized for use as inverter buffers for driving TTL inputs. The ?LS06 has a rated output voltage of 30 V and the ?LS16 has a rated output voltage of 15 V. The maximum sink current for the 74LS06  is 40 mA. The circuits is compatible with most TTL families. Inputs are diode-clamped to minimize transmission-effects, which simplifies design. Typical power dissipation is 175 mW and average propagation delay time is 8 ns. The 74LS06 is characterized for operation from 0?C to 70?C.

The 74LS06 SMD device contains hex inverted buffers with open-collector. It performs the Boolean function Y=A in positive Logic:-

The 74LS10 contains three independent gates each of which performs the logic NAND function.

The 74LS109 devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together. 

The 74LS109 devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together. The 74LS109 is characterized for operation from 0?C to 70?C. The feature of 74LS109 is a package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs

The 74LS11 devices contain three independent 3-input NAND gates. The 74LSI1 is characterized for operation from O ?C to 70 ?C.