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This device contains six independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capability to permit the driving of bus lines without external resistors. When disabled, both the output transistors are turned OFF presenting a high-impedance state to the bus line. Thus the output will act neither as a significant load nor as a driver. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable time of the outputs

This device contains six independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capability to permit the driving of bus lines without external resistors. When disabled, both the output transistors are turned OFF presenting a high-impedance state to the bus line. Thus the output will act neither as a significant load nor as a driver. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable time of the outputs

These Hex buffers and line drivers are designed specifically to improve both the performance and density of three-state memory address drivers, clock drivers, and bus oriented receivers and transmitters. The designer has choice of selected combinations of inverting and noninverting outputs, symmetrical G (active-low control) inputs. These devices feature high fan-out, improved fan-in, and can be used to drive terminated lines down to 133 ohms.

These Hex buffers and line drivers are designed specifically to improve both the performance and density of three-state memory address drivers, clock drivers, and bus oriented receivers and transmitters. The designer has choice of selected combinations of inverting and noninverting outputs, symmetrical G (active-low control) inputs. These devices feature high fan-out, improved fan-in, and can be used to drive terminated lines down to 133 ohms.

The 74LS379 is a 4-Bit Register with buffered common Enable. This device is similar to the 74LS175 but features the common Enable rather then common Master Reset.

This device contains four independent gates, each of which performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation.

This device contains four independent gates, each of which performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation.

The 74LS399 are Quad 2-Port Registers. They are the logical equivalent of a quad 2-input multiplexer followed by a quad 4-bit edge-triggered register. A Common Select input selects between two 4-bit in put ports (data sources). The selected data is transferred to the output register on the LOW-to-HIGH transition of the Clock input. The 74LS398 features Q and Q inputs, while the 74LS399 has only Q outputs.