Showing 1861–1872 of 3753 results
74LS90 IC ? (SMD Package) – Decade Counter IC (7490 IC)
The 74LS90 is a 4-bit ripple type counters partitioned into two sections. Each counter has a divide-by-two section and either a divide-by-five (LS90) section which are triggered by a HIGH-to-LOW transition on the clock inputs. Each section can be used separately or tied together (Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of the counters have a 2-input gated Master Reset (Clear), and the LS90 also has a 2-input gated Master Set. The following are the features:-
74LS95 4-bit Parallel-Access Shift Register IC (7495 IC) DIP-14 Package
The 74LS95 is a 4-Bit Shift Register with serial and parallel synchronous operating modes. The serial shift right and parallel load are activated by separate clock inputs which are selected by a mode control input. The data is transferred from the serial or parallel D inputs to the Q outputs synchronous with the HIGH to LOW transition of the appropriate clock input. The LS95B is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families.
74LS95 IC – (SMD Package) – 4-bit Parallel-Access Shift Register IC (7495 IC)
The 74LS95 is a 4-Bit Shift Register with serial and parallel synchronous operating modes. The serial shift right and parallel load are activated by separate clock inputs which are selected by a mode control input. The data is transferred from the serial or parallel D inputs to the Q outputs synchronous with the HIGH to LOW transition of the appropriate clock input. The 74LS95 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families. The following are the features:-
74LS96 5-Bit Shift Register IC (7496 IC) DIP-16 Package
The 74LS96 is a 5-bit shift register with both serial and parallel (ones transfer) data entry. Since the '96 has the output of each stage available as well as a D-type serial input and ones transfer inputs on each stage, it can be used 5-bit serial- to-parallel, serial-to-serial and some parallel-to-serial data operations. The 74LS96 is five master/slave flip-flops connected to perform right shift. The flip- flops change state on the LOW-HIGH transition of the clock. The Serial (S) input is edge-triggered and must be stable only one set-up time before the LOW to HIGH clock transition.
74LS96 IC – (SMD Package) – 5-Bit Shift Register IC (7496 IC)
The 74LS96 is a shift registers consist of five RS master-slave flip-flops connected to perform parallel-to-serial or serial to parallel conversion of binary data. Since both inputs and outputs for all flip-flops are accessible parallel-in/parallel-out serial in/serial out operation may be performed.
74LS962 Dual Rank 8-Bit Tri-State Shift Register IC (74962 IC) DIP-16 Package
These circuits are TRI-STATE, edge-triggered, 8-bit I/O registers in parallel with 8-bit serial shift registers which are capable of operating in any of the following modes: parallel load from I/O pins to register ??A??, parallel transfer down from register ??A?? to serial shift register ??B??, parallel transfer up from shift register ??B?? to register ??A??, serial shift of register ??B??, or exchange data between register ??A?? and shift register ??B??. Since the registers are edge-triggered by the positive transition of the clock, the control lines which determine the mode or operation are completely independent of the logic level applied to the clock. Designed for bus-oriented systems, these circuits have their TRI-STATE inputs and outputs on the same pins.
74LS962 IC – (SMD Package) – Dual Rank 8-Bit Tri-State Shift Register IC (74962 IC)
These circuits are TRI-STATE, edge-triggered, 8-bit I/O registers in parallel with 8-bit serial shift registers which are capable of operating in any of the following modes: parallel load from I/O pins to register ??A??, parallel transfer down from register ??A?? to serial shift register ??B??, parallel transfer up from shift register ??B?? to register ??A??, serial shift of register ??B??, or exchange data between register ??A?? and shift register ??B??. Since the registers are edge-triggered by the positive transition of the clock, the control lines which determine the mode or operation are completely independent of the logic level applied to the clock. Designed for bus-oriented systems, these circuits have their TRI-STATE inputs and outputs on the same pins.
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