74HC93 IC – (SMD Package) – 4-Bit Binary Ripple Counter IC (7493 IC)
The 74HC93 are high-speed silicon-gate CMOS devices and are pin-compatible with low power Schottky TTL (LSTTL). These 4-bit binary ripple counters consist of four master-slave flip-flops internally connected to provide a divide-by-two section and a divide- by-eight section. Each section has a separate clock input (CP0 and CP1) to initiate state changes of the counter on the HIGH to LOW clock transition. State changes of the Qn outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. A gated AND asynchronous master reset (MR1 and MR2 is provided which overrides both clocks and resets (clears) all flip-flops. Because the output from the divide by two section is not internally connected to the succeeding stages, the device may be operated in various counting modes. In a 4-bit ripple counter the output Q0 must be connected externally to input CP1. The input count pulses are applied to clock input CP0. Simultaneous frequency divisions of 2, 4, 8, and 16 are performed at the Q0, Q1, Q2, and Q3 outputs as shown in the function table. As a 3-bit ripple counter the input count pulses are applied to input CP1. Simultaneous frequency divisions of 2, 4, and 8 are available at the Q1, Q2, Q3 outputs. Independent use of the first flipflop is available if the reset function coincides with the reset of the 3-bit ripple-through counter.
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Description
The 74HC93 are high-speed silicon-gate CMOS devices and are pin-compatible with low power Schottky TTL (LSTTL). These 4-bit binary ripple counters consist of four master-slave flip-flops internally connected to provide a divide-by-two section and a divide- by-eight section. Each section has a separate clock input (CP0 and CP1) to initiate state changes of the counter on the HIGH to LOW clock transition. State changes of the Qn outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. A gated AND asynchronous master reset (MR1 and MR2 is provided which overrides both clocks and resets (clears) all flip-flops. Because the output from the divide by two section is not internally connected to the succeeding stages, the device may be operated in various counting modes. In a 4-bit ripple counter the output Q0 must be connected externally to input CP1. The input count pulses are applied to clock input CP0. Simultaneous frequency divisions of 2, 4, 8, and 16 are performed at the Q0, Q1, Q2, and Q3 outputs as shown in the function table. As a 3-bit ripple counter the input count pulses are applied to input CP1. Simultaneous frequency divisions of 2, 4, and 8 are available at the Q1, Q2, Q3 outputs. Independent use of the first flipflop is available if the reset function coincides with the reset of the 3-bit ripple-through counter.
Features:-
? Can Be Configured to Divide By 2, 8, and 16
? Asynchronous Master Reset
? Fanout (Over Temperature Range)
– Standard Outputs 10 LSTTL Loads
– Bus Driver Outputs 15 LSTTL Loads
? Wide Operating Temperature Range -55? C to 125? C
? Balanced Propagation Delay and Transition Times
? Significant Power Reduction Compared to LSTTL Logic ICs
? HC Types
– 2V to 6V Operation
– High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
? HCT Types
– 4.5V to 5.5V Operation
– Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)
– CMOS Input Compatibility, Il ? 1?A at VOL, VOH
Specification:-
| Symbol | Parameter | Value | Unit |
| VCC | Supply Voltage | ? 0.5 to + 7.0V | V |
| IIK | DC Input Diode Current | ?20 | mA |
| IOK | DC Output Diode Current | ?20 | mA |
| IO | Output Current | ? 25 | mA |
| ICC or IGND | DC VCC or GND Current, per pin | 50 | mA |
| TSTG | Storage Temperature Range | ? 55?C to + 150 | ?C |
Related Document:-
Additional information
Operating voltage | 2.5 3.0V |
Pixel Resolution | 0.3MP |
Photosensitive array | 640 x 480 |
Optical Size | 1.6 inch |
Angel of view | 67 degrees |
Maximum Frame Rate | 30fps VGA |
Sensitivity | 1.3V/(Lux-sec) |
Dormancy | Less than 20A |
Power consumption | 60mW/15fpsVGA YUV |
Temperature operation Range | -30 C ~ 70 C |
Pixel area | 3.6 x 3.6 m |
Signal to noise ratio (SNR) | 46 dB |
Dynamic range | 52 dB |


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