CD4012 Dual 4-Input NAND Gate IC DIP-14 Package
The NAND gate is monolithic complementary MOS (CMOS) integrated circuits. The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swings essentially equal to the supply voltage. This results in high noise immunity over a wide supply voltage range. No DC power other than that caused by leakage current is consumed during static conditions. All inputs are protected against static discharge and latching conditions.
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Description
The NAND gate is monolithic complementary MOS (CMOS) integrated circuits. The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swings essentially equal to the supply voltage. This results in high noise immunity over a wide supply voltage range. No DC power other than that caused by leakage current is consumed during static conditions. All inputs are protected against static discharge and latching conditions.
Features:-
- Two Independent 4-input NAND Gates
- Standard Pin Configuration
- Wide Operating Voltage Range
- Operating Temperature to 85?C
- Low Power CMOS
Specifications:-
| Parameter | Specification |
| Voltage at Any Pin | VSS -0.3V to VDD +0.3V |
| Operating Temperature Range | -40?C to + 85?C |
| Storage Temperature Range (TS) | -65?C to +150?C |
| Power Dissipation (PD): Dual-In-Line | 700 mW |
| Operating Range (VDD) | VSS +3.0V to VSS +15V |
| Lead Temperature (TL) | 260?C |
(For detailed specification refer Data Sheet)
Related Document:-
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Additional information
Operating voltage | 2.5 3.0V |
Pixel Resolution | 0.3MP |
Photosensitive array | 640 x 480 |
Optical Size | 1.6 inch |
Angel of view | 67 degrees |
Maximum Frame Rate | 30fps VGA |
Sensitivity | 1.3V/(Lux-sec) |
Dormancy | Less than 20A |
Power consumption | 60mW/15fpsVGA YUV |
Temperature operation Range | -30 C ~ 70 C |
Pixel area | 3.6 x 3.6 m |
Signal to noise ratio (SNR) | 46 dB |
Dynamic range | 52 dB |
Specification
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