Showing 181–192 of 700 results
74HC646 Octal Bus Transceiver Register IC (74646 IC) DIP-24 Package
The M74HC646 are high speed CMOS OCTAL BUS TRANSCEIVERS AND REGISTERS, (3-STATE) fabricated in silicon gate C2 MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low power consumption. These devices consist of bus transceiver circuits with 3-state output, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers on the low-to-high transition of the appropriate clock pin (Clock AB - or Clock BA). Enable(G) and direction (DIR) pins are provided to control the
74HC73 Dual J-K Negative-Edge-Triggered Flip-Flops IC (7473) DIP-14 Package
The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable, one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (nR) is asynchronous, when LOW it overrides the clock and data inputs, forcing the nQ output LOW and the nQ output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC
74HC73 IC – (SMD Package) – Dual J-K Negative-Edge-Triggered Flip-Flops IC (7473)
The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. The 74HC is a dual negative-edge triggered JK flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the nQ output LOW and the nQ output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
74HC75 4 Bit Bi-Stable Latch IC (7475 IC) DIP-16 Package
74HC75 is 4 Bit Bi-Stable Latch 16 Pin IC. It contains 4 transparent D latches with common enable (gate) on latches 0 and 1 and another common enable on latches 2 and 3. When Q follows D (latch enabled) latch is said to be transparent. Q output will change only on edge of input trigger pulse. small triangle on clock (Cp) input of symbol indicates that device is positive edge-triggered. D and clock inputs are synchronous inputs. set (SD) and reset (RD) inputs are asynchronous. They operate independent of D and Cp. bubbles on set and reset inputs indicate that they are low active. latches are ideally suited for use as temporary storage for binary information between processing units and input output or indicator units.
74HC75 IC – (SMD Package) – 4 Bit Bi-Stable Latch IC (7475 IC)
The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs (nD) as long as LEnn is HIGH (transparent). The data on the nD inputs one set-up time prior to the HIGH-to-LOW transition of the LEnn will be stored in the latches. The latched outputs remain stable as long as the LEnn is LOW.
74HC85 4-bit Magnitude Comparator IC (7485 IC) DIP-16 Package
The 74HC85 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC85 are 4-bit magnitude comparators that can be expanded to almost any length. They perform comparison of two 4-bit binary, BCD or other monotonic codes and present the three possible magnitude results at the outputs (QA>B, QA=B and QAB, IA=B and IAB = = LOW and IA=B = HIGH. For words greater than 4-bits, units can be cascaded by connecting outputs QA? and QA=B to the corresponding inputs of the significant comparator.
74HC85 IC – (SMD Package) – 4-bit Magnitude Comparator IC (7485 IC)
The 74HC85 SMD is a 4-bit magnitude comparator that can be expanded to almost any length. They perform comparison of two 4-bit binary, BCD or other monotonic codes and present the three possible magnitude results at the outputs (QA>B, QA=B and QAB, IA=B and IAB = LOW and IA=B = HIGH. For words greater than 4-bits, units can be cascaded by connecting outputs QA>B, QA=B and QA.
74HC86 IC – (SMD Package) – Quad 2-Input EXOR Gate IC (7486 IC)
74HC86 is Quad 2-Input EXOR Gate 14 Pin SMD IC. It is an advanced high speed CMOS 2?input Exclusive?OR gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. Internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. Inputs tolerate voltages up to 7V, allowing interface of 5V systems to 3V systems. Used for Building Arithmetic Logic Circuits, Computational Logic Comparators and Error Detection Circuits and True/Complement Element.
74HC86 Quad 2-Input EXOR Gate IC (7486 IC) DIP-14 Package
74HC86 is Quad 2-Input EXOR Gate 14 Pin IC. It is an advanced high speed CMOS 2?input Exclusive?OR gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. Internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. Inputs tolerate voltages up to 7V, allowing interface of 5V systems to 3V systems. Used for Building Arithmetic Logic Circuits, Computational Logic Comparators and Error Detection Circuits and True/Complement Element.
74HC93 4-Bit Binary Ripple Counter IC (7493 IC) DIP-14 Package
The 74HC93 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC93 are 4-bit binary ripple counters. The devices consist of four master-slave flip-flops internally connected to provide a divide-by-two section and a divide-by-eight section. Each section has a separate clock input (CP0 and CP1) to initiate state changes of the counter on the HIGH-to-LOW clock transition. State changes of the Qn outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes.
74HC93 IC – (SMD Package) – 4-Bit Binary Ripple Counter IC (7493 IC)
The 74HC93 are high-speed silicon-gate CMOS devices and are pin-compatible with low power Schottky TTL (LSTTL). These 4-bit binary ripple counters consist of four master-slave flip-flops internally connected to provide a divide-by-two section and a divide- by-eight section. Each section has a separate clock input (CP0 and CP1) to initiate state changes of the counter on the HIGH to LOW clock transition. State changes of the Qn outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. A gated AND asynchronous master reset (MR1 and MR2 is provided which overrides both clocks and resets (clears) all flip-flops. Because the output from the divide by two section is not internally connected to the succeeding stages, the device may be operated in various counting modes. In a 4-bit ripple counter the output Q0 must be connected externally to input CP1. The input count pulses are applied to clock input CP0. Simultaneous frequency divisions of 2, 4, 8, and 16 are performed at the Q0, Q1, Q2, and Q3 outputs as shown in the function table. As a 3-bit ripple counter the input count pulses are applied to input CP1. Simultaneous frequency divisions of 2, 4, and 8 are available at the Q1, Q2, Q3 outputs. Independent use of the first flipflop is available if the reset function coincides with the reset of the 3-bit ripple-through counter.
74LS00 Quad 2 Input NAND Gate IC (7400 IC) DIP-14 Package
The 74LS00 is a 14 Pin Quad 2-Input NAND Gate IC. This device contains four independent gates each of which performs the logic NAND function. NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds with the low power consumption of standard CMOS integrated circuits. All gates have buffered outputs.
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