Electronic Components

These monolithic, positive-edge-triggered flipflops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect ar the output. These flip-flops are guaranteed to respond to clock frequencies ranging form 0 to 30 megahertz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 39 milliwatts per flip-flop for the ?273 and 10 milliwatts for the ?LS273.

These monolithic, positive-edge-triggered flipflops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect ar the output. These flip-flops are guaranteed to respond to clock frequencies ranging form 0 to 30 megahertz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 39 milliwatts per flip-flop for the ?273 and 10 milliwatts for the ?LS273.

The 74LS280 IC designed as a Universal 9-Bit Parity Generator /Checker. These IC provides odd/ even outputs to facilitate either odd or even parity. By cascading, the word length is easily expanded. The 74LS280 IC operates at a wide range of working voltage, a wide range of working conditions. And directly interfaces with CMOS, NMOS, and TTL. The output of the IC always comes in TTL which makes it quite easy to function with other TTL devices and microcontrollers. The IC 74LS280 comes as smaller in size and offers much faster speed which makes it highly reliable in every kind of device.

The 74LS280 IC designed as a Universal 9-Bit Parity Generator /Checker. These IC provides odd/ even outputs to facilitate either odd or even parity. By cascading, the word length is easily expanded. The 74LS280 IC operates at a wide range of working voltage, a wide range of working conditions. And directly interfaces with CMOS, NMOS, and TTL. The output of the IC always comes in TTL which makes it quite easy to function with other TTL devices and microcontrollers. The IC 74LS280 comes as smaller in size and offers much faster speed which makes it highly reliable in every kind of device.

The 74LS298 is a Quad 2-Port Register. It is the logical equivalent of a quad 2-input multiplexer followed by a quad 4-bit edge-triggered register. A Common Select input selects between two 4-bit input ports (data sources.) The selected data is transferred to the output register synchronous with the HIGH to LOW transition of the 

The 74LS298 is a Quad 2-Port Register. It is the logical equivalent of a quad 2-input multiplexer followed by a quad 4-bit edge-triggered register. A Common Select input selects between two 4-bit input ports (data sources.) The selected data is transferred to the output register synchronous with the HIGH to LOW transition of the 

The 74LS299 is an 8-bit universal shift/storage register with 3-STATE outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Separate outputs are provided for flip-flops Q0 and Q7 to allow easy cascading. A separate active LOW Master Reset is used to reset the register

The 74LS299 is an 8-bit universal shift/storage register with 3-STATE outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Separate outputs are provided for flip-flops Q0 and Q7 to allow easy cascading. A separate active LOW Master Reset is used to reset the register