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CD4029 Binary Decade Up-Down Counter IC DIP-16 Package

41.30
CD4029 consists of a four-stage binary or BCD-decade up/ down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN (CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT signal are provided as outputs.

CD4030 Quad 2-Input Exclusive OR (EXOR) Gate IC DIP-14 Package

21.24
CD4030 types consist of four independent Exclusive-OR gates. THe CD4030 provides the system designer with a means for direct implementation of the Exclusive-OR function.

CD4033 5-Stage Johnson Decade counter IC DIP-16 Package

210.04
CD4033 consist of a 5-stage Johnson decade counter and an output decoder which converts the Johnson code to a 7-segment decoded output for driving one stage in a numerical display.

CD4034 8-Stage Bidirectional Bus Register IC DIP-24 Package

93.22
CD4034 is a static eight-stage parallel-or serial-input parallel-output register. It can be used to:

CD4040 12-Stage Ripple Carry Binary Counter IC DIP-16 Package

29.50
CD4040 is ripple-carry binary counters. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times. All inputs and outputs are buffered.

CD4043 IC – (SMD Package) – Quad NOR R-S Latch Tri-state IC

29.50
The CD4043 is a CMOS quad NOR R/S Latch with 3-state outputs. Each latch has a separate Q output and

CD4043 Quad NOR R-S Latch Tri-state IC DIP-16 Package

31.86
The CD4043 is quad cross-couple 3-STATE CMOS NOR latches These latch has a separate Q output and individual SET and RESET inputs. There is a common 3-STATE ENABLE input for all four latches. A logic ?1? on the ENABLE input connects the latch states to the Q outputs. A logic ?0? on the ENABLE input disconnects the latch states from the Q outputs resulting in an open circuit condition on the Q output. The 3-STATE feature allows common bussing of the outputs. 

CD4046 Micropower Phase Locked Loop IC DIP-16 Package

25.96
CD4046 CMOS Micropower Phase-Locked Loop (PLL) consists of a low-power, linear voltage-controlled oscillator (VCO) and two different phase comparators having a common signal-input amplifier and a common comparator input. A 5.2-V zener diode is provided for supply regulation if necessary.

CD4047 Astable/Monostable Multivibrator IC DIP-14 Package

21.24
CD4047 consists of a gatable astable multivibrator with logic techniques incorporated to permit positive or negative edge-triggered monostable multivibrator action with retriggering and external counting options.

CD4049 Hex Inverting Buffer/Converter IC DIP-16 Package

18.88
The CD4049 device are inverting hex buffers, and feature logic-level conversion using only one supply voltage (VCC). The input-signal high level (VIH) can exceed the VCC supply voltage when these devices are used for logic-level conversions. These devices are intended for use as CMOS to DTL or TTL converters and can drive directly two DTL or TTL loads. (VCC = 5 V, VOL ? 0.4 V, and IOL ? 3.3 mA.)

CD4050 Hex Non-Inverting Buffer IC DIP-16 Package

20.06
The CD4050 devices noninverting hex buffers, and feature logic-level conversion using only one supply voltage (VCC). The input-signal high level (VIH) can exceed the VCC supply voltage when these devices are used for logic-level conversions. These devices are intended for use as CMOS to DTL or TTL converters and can drive directly two DTL or TTL loads. (VCC = 5 V, VOL ? 0.4 V, and IOL ? 3.3 mA.)

CD4051 Single 8-channel Multiplexer/Demultiplexer IC DIP-16 Package

22.42
The CD4051 analog multiplexers and demuliplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current. These multiplexer circuits dissipate extremely low quiescent power over the full VDD ? VSS and VDD ? VEE supply-voltage ranges, independent of the logic state of the control signals.