CD4027 Dual JK Flip Flop IC DIP-16 Package

CD4027 is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K master-slave flip-flops. Each flip-flop has provisions for individual J, K, Set, Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-ouput arrangement provides for compatible operation with the RCA-CD4013B dual D-type flip-flop.

SKU: RW-02311

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Description

CD4027 is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K master-slave flip-flops. Each flip-flop has provisions for individual J, K, Set, Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-ouput arrangement provides for compatible operation with the RCA-CD4013B dual D-type flip-flop.

The CD4027 is useful in performing control, register, and toggle functions. Logic levels present at the J and K inputs along with internal self-steering control the state of each flip-flop; changes in the flip-flop state are synchronous with the positive-going transition of the clock pulse. Set and reset functions are independent of the clock and are initiated when a high level signal is present at either the Set or Reset input.

The CD4027 types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

Features:-

  • Set-Reset capability
  • Static flip-flop operation ? retains state indefinitely with clock level either “high” or “low”
  • Medium speed operation ? 16 MHz (typ.) clock toggle rate at 10 V
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 ?A at 18 V over full package-temperature range; 100 nA at 18 V and 25?C
  • Noise margin (full package-temperature range) =
        1 V at VDD = 5 V
        2 V at VDD = 10 V
        2.5 V at VDD = 15 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ?B? Series CMOS Devices”
  • Applications:
    • Registers, counters, control circuits


Specifications:-

Parameter Specification
Part number CD4027B
Technology Family CD4000
VCC (Min) (V) 3
VCC (Max) (V) 18
Bits (#) 2
Voltage (Nom) (V) 10
F @ nom voltage (Max) (MHz) 8
ICC @ nom voltage (Max) (mA) 0.06
tpd @ nom Voltage (Max) (ns) 130
IOL (Max) (mA) 1.5
IOH (Max) (mA) -1.5
Rating See Data Sheet

Related Document:-

 CD4027 IC Datasheet


Additional information

Operating voltage

2.5 3.0V

Pixel Resolution

0.3MP

Photosensitive array

640 x 480

Optical Size

1.6 inch

Angel of view

67 degrees

Maximum Frame Rate

30fps VGA

Sensitivity

1.3V/(Lux-sec)

Dormancy

Less than 20A

Power consumption

60mW/15fpsVGA YUV

Temperature operation Range

-30 C ~ 70 C

Pixel area

3.6 x 3.6 m

Signal to noise ratio (SNR)

46 dB

Dynamic range

52 dB

Specification

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