Electronic Components

The 74HC590 is an 8-bit binary counter with a storage register and 3-state outputs. The storage register has parallel (Q0 to Q7) outputs. The binary counter features master reset counter (MRC) and count enable (CE) inputs. The counter and storage register have separate positive edge triggered clock (CPC and CPR) inputs. If both clocks are connected together, the counter state is always one count ahead of the register. Internal circuitry prevents clocking from the clock enable. A ripple carry output (RCO) is provided for cascading. Cascading is accomplished by connecting RCO of the first stage to CE of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage to the counter clock (CPC) input of the following stage. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The 74HC595 high speed shift register utilizes advanced silicon-gate CMOS technology. This device possesses the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has 8 3-STATE outputs. Separate clocks are provided for both the shift register and the storage register.

The M74HC646 are high speed CMOS OCTAL BUS TRANSCEIVERS AND REGISTERS, (3-STATE) fabricated in silicon gate C2 MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low power consumption. These devices consist of bus transceiver circuits with 3-state output, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers on the low-to-high transition of the appropriate clock pin (Clock AB - or Clock BA). Enable(G) and direction (DIR) pins are provided to control the

The M74HC646 are high speed CMOS OCTAL BUS TRANSCEIVERS AND REGISTERS, (3-STATE) fabricated in silicon gate C2 MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low power consumption. These devices consist of bus transceiver circuits with 3-state output, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers on the low-to-high transition of the appropriate clock pin (Clock AB - or Clock BA). Enable(G) and direction (DIR) pins are provided to control the

74HC75 is 4 Bit Bi-Stable Latch 16 Pin IC. It contains 4 transparent D latches with common enable (gate) on latches 0 and 1 and another common enable on latches 2 and 3. When Q follows D (latch enabled) latch is said to be transparent. Q output will change only on edge of input trigger pulse. small triangle on clock (Cp) input of symbol indicates that device is positive edge-triggered. D and clock inputs are synchronous inputs. set (SD) and reset (RD) inputs are asynchronous. They operate independent of D and Cp. bubbles on set and reset inputs indicate that they are low active. latches are ideally suited for use as temporary storage for binary information between processing units and input output or indicator units.

The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs (nD) as long as LEnn is HIGH (transparent). The data on the nD inputs one set-up time prior to the HIGH-to-LOW transition of the LEnn will be stored in the latches. The latched outputs remain stable as long as the LEnn is LOW.

The 74HC85 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC85 are 4-bit magnitude comparators that can be expanded to almost any length. They perform comparison of two 4-bit binary, BCD or other monotonic codes and present the three possible magnitude results at the outputs (QA>B, QA=B and QAB, IA=B and IAB = = LOW and IA=B = HIGH. For words greater than 4-bits, units can be cascaded by connecting outputs QA? and QA=B to the corresponding inputs of the significant comparator. 

The 74HC85 SMD is a 4-bit magnitude comparator that can be expanded to almost any length. They perform comparison of two 4-bit binary, BCD or other monotonic codes and present the three possible magnitude results at the outputs (QA>B, QA=B and QAB, IA=B and IAB = LOW and IA=B = HIGH. For words greater than 4-bits, units can be cascaded by connecting outputs QA>B, QA=B and QA.