Electronic Components

The 74LS10 devices contain three independent 3-input NAND gates. The 74LSI0 is characterized for operation from O ?C to 70 ?C.

The 74LS10 contains three independent gates each of which performs the logic NAND function.

The 74LS109 devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together. 

The 74LS109 devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together. The 74LS109 is characterized for operation from 0?C to 70?C. The feature of 74LS109 is a package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs

The 74LS12 Triple 3-Input Positive NAND Gates With Collector Outputs contains three 3 input independent gates each of which performs the positive logic NAND function. 74LS12 IC can be soldered directly to the circuit board or can be mounted on a 14 pin IC base. 74LS12 Triple 3-Input Positive NAND Gates With Collector Outputs circuit is designed such that the operation produced on the inputs of pin are (1 & 2 & 3 & 4 NAND 10 & 11 & 12 & 13) is produced on the pin 8 . Operating supply voltages to the IC can vary between 4.5V to 5V and to a maximum of 5.5V and the input logic levels to the device in ?0? (LOW) state is max. 0.7V and for ?1? (HIGH) state is min 2V.

74LS12 Triple 3-Input Positive NAND Gate IC (7412 IC) DIP-14 Package

These dc triggered multivibrators feature pulse width control by three methods. The basic pulse width is programmed by selection of external resistance and capacitance values. The LS122 has an internal timing resistor that allows the circuits to be used with only an external capacitor. Once triggered, the basic pulse width may be extended by retriggering the gated low-level-active (A) or high-level-active (B) inputs, or be reduced by use of the overriding clear.

These dc triggered multivibrators feature pulse width control by three methods. The basic pulse width is programmed by selection of external resistance and capacitance values. The LS122 has an internal timing resistor that allows the circuits to be used with only an external capacitor. Once triggered, the basic pulse width may be extended by retriggering the gated low-level-active (A) or high-level-active (B) inputs, or be reduced by use of the overriding clear.